1. Field of the Invention
The present invention relates to a semiconductor manufacturing process, and more particularly, to a method of reducing the aspect ratio of a trench.
2. Description of the Related Art
Semiconductor device geometry continues to decrease in size, providing more devices per fabricated wafer. Currently, some devices are fabricated with less than 0.25 μm spacing between features; in some cases there is as little as 0.18 μm spacing between features, which often takes the form of a trench.
An isolation technique called shallow trench isolation (STI) has been introduced to the fabrication of devices to reduce size. Isolation trenches are formed in a substrate between features, such as transistors. FIGS. 1A-1B are schematic views of a traditional STI process.
In FIG. 1A, a substrate 10 such as a silicon wafer is provided. A shield layer 11 composed of a pad oxide layer 12 and a silicon nitride layer 14 is formed on part of the substrate 10. The shield layer 11 serves as a stacked mask defining an isolation area in the substrate 10. The pad oxide layer 12 can be a SiO2 layer with a thickness of 50˜150 Å, formed by chemical vapor deposition (CVD) or thermal oxidation. The silicon nitride layer 14 can be a Si3N4 layer with a thickness of 800˜1500 Å, formed by CVD.
In FIG. 1B, using the shield layer 11 as a mask, part of the substrate 10 is etched to form a trench 15. A thin oxide film 16, serving as a linear layer, is then formed by thermal oxidation, conformal to the surface of the trench 15. The thickness of the thin oxide film 16 is about 180˜220 Å. Next, a trench-filling material such as a SiO2 layer 18 is deposited in the trench 15 once with a conventional high-density plasma chemical vapor deposition (HDP-CVD). Typically, the HDP-CVD reaction gas includes O2 and silane (SiH4).
FIG. 1C shows that a void may form when a trench with a narrow gap is filled by traditional process. For example, when the width of the trench 15 is less than 0.15 μm and/or the aspect ratio of the trench is greater than 4, a void 20 is easily formed in a SiO2 layer 19 with the traditional process. Such a void 20 seriously affects device reliability and yield, and hinders reduction in semiconductor device geometry.